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IEEE Defect and Adaptive Test Analysis Workshop
(DATA 2011)

September 22-23, 2011
Anaheim, CA, USA

http://data.tttc-events.org/

SUBMISSION DEADLINE JULY 21st!
CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

New initiatives in getting more out of testing have opened up new avenues of research and development in the areas of extracting information about defects and IC behavior through the use of innovative analysis techniques. As the need for these novel processes is becoming more widely accepted in the industry, new questions about how these techniques should be executed and controlled  in production, the types and sizes of database requirements, and even the format of test data and storage itself are being reviewed and discussed. New issues such as the control and documentation of dynamic test changes in response to local test data, ensuring high quality levels without test escapes, and the practical and realistic limitations of these new ideas are for board/system are now being discussed by many people in the industry. Even the definition of what is “Adaptive testing” is still being reviewed and defined. Closing the knowledge gap about these issues, the process, new test techniques, database requirements, and how defect models are being used to adapt test flows will be the goals of this year’s DATA workshop.

The IEEE International Workshop on Defect & Adaptive Test Analysis (DATA 2011) is aimed at addressing the above issues. Paper presentations on topics related to the topics listed below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

Outlier Identification 
Data-Driven Testing (DDT)
Test Data Analysis
Yield Learning and Analysis Using DDT
Adaptive Test Database requirements
Data-Mining Methods for Test Data Processing
High/Low Voltage Testing & Stress Testing
Transition and Delay Fault Testing

Reliability and Yield
Nanometer Test Challenges
Defect Coverage & Metrics
Mixed Current/Voltage Testing
Economics of Defect Based Testing
Fault Localization & Diagnosis
Noise and Crosstalk Testing
In-System or On-board Testing

 

Submissions

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To present at the workshop, submit a PDF version of an extended abstract of at least 1000 words or a full paper (Max 8 pages, double column, 11pt font size, IEEE proceeding format) by July 21, 2011. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Aug 30, 2011. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.

Technical Program Submissions:
Jeff Roehr
Texas Instruments

E-mail: JLRoehr@Gmail.com

 

Key Dates

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Submission deadline: July 21, 2011
Notification of acceptance: August 10, 2011
Final copy deadline: August 30, 2011

Additional Information
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General Information

Sankaran Menon
Intel Corp.

E-mail: Sankaran.Menon@intel.com

Committees
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General Chair
Sankaran M. Menon, Intel

Co-General Chair
Al Crouch, Asset-Intertech

Program Chair
Jeff Roehr, Texas Instruments

Co-Program Chair
Arani Sinha, AMD

Vice Program Chair
Nisar Ahmed, Freescale

Finance Chair
Sankaran M. Menon, Intel

Publicity Chair
Jennifer Dworak, SMU

Publication Chair
Chintan Patel, UMBC

Steering Committee
Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Start Test
Jim Plusquellic, U. New Mexico

Program Committee
Rob Aitken, ARM
Tom Bartenstein, Cadence
Nemat Bidokhti, Cisco
Ken Butler, TI
Krish Chakrabarty, Duke Univ.
Sreejit Chakravarty, LSI Logic
John Carulli, TI
Bruce Cory, Nvidia
Jennifer Dworak, Brown University
Patrick Girard, LIRRM
Sandeep Goel, TSMC
Rohit Kapur, Synopsys
Ajay Koche, Consultant
Mike Laisne, Qualcomm
Nilanjan Mukherjee, Mentor Graphics
Teresa McLaurin, ARM
Amit Nahar, TI
Suriyaprakash Natarajan, Intel  
Jay Orbon, Verigy
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Mani Soma, U Washington
Claude Thibeault, Ecole Tech
Li C. Wang, UCSB              
Xiaoqing Wen, Kyushu Institute of Tech.
LeRoy Winemberg, Freescale
Qiang Xu, CUHK
Mahmut Yilmaz, AMD

For more information, visit us on the web at: http://data.tttc-events.org/

The Defect and Adaptive Test Analysis Workshop (DATA 2011 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Ron PRESS
Mentor Graphics - USA
Tel. +1-
E-mail ron_press@mentor.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com